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INTEGRATED CIRCUITS
DATA SHEET
PCF8531 34 x 128 pixel matrix driver
Product specification Supersedes data of 1999 Aug 10 File under Integrated Circuits, IC12 2000 Feb 11
Philips Semiconductors
Product specification
34 x 128 pixel matrix driver
CONTENTS 1 2 3 4 5 6 7 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.12 8.13 8.14 8.15 8.16 8.17 8.18 8.18.1 8.18.2 8.18.3 8.18.4 8.18.5 8.18.6 8.18.7 8.18.8 8.18.9 8.18.10 8.18.11 FEATURES APPLICATIONS GENERAL DESCRIPTION PACKAGES ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Oscillator Power-on reset I2C-bus controller Input filters Display data RAM Timing generator Address counter Display address counter Command decoder Bias voltage generator VLCD generator Reset Power-down Column driver outputs Row driver outputs LCD waveforms and DDRAM to data mapping Addressing Instructions Reset Function set Set Y address Set X address Set multiplex rate Display control (D, E and IM) Set bias system LCD bias voltage Set VOP value: Voltage multiplier control S[1:0] Temperature compensation 9 9.1 9.1.1 9.1.2 9.1.3 9.1.4 9.2 9.3 10 11 12 13 14 15 16 17 18 19 20 I2C-BUS INTERFACE Characteristics of the I2C-bus Bit transfer START and STOP conditions System configuration Acknowledge I2C-bus protocol Command decoder LIMITING VALUES HANDLING DC CHARACTERISTICS AC CHARACTERISTICS
PCF8531
APPLICATION INFORMATION BONDING PAD LOCATIONS DEVICE PROTECTION DIAGRAM TRAY INFORMATION DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2C COMPONENTS
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Philips Semiconductors
Product specification
34 x 128 pixel matrix driver
1 FEATURES
PCF8531
* Single-chip LCD controller/driver * 34 row and 128 column outputs * Display data RAM 34 x 128 bits * 128 icons (last row is used for icons) * Fast mode I2C-bus interface (400 kbit/s) * Software selectable multiplex rates: 1 : 17, 1 : 26 and 1 : 34 * Icon mode with Mux rate 1 : 2: - Featuring reduced current consumption while displaying icons only. * On-chip: - Generation of VLCD (external supply also possible) - Selectable linear temperature compensation - Oscillator requires no external components (external clock also possible) - Generation of intermediate LCD bias voltages - Power-on reset. * No external components required * Software selectable bias configuration * Logic supply voltage range VDD1 to VSS1 1.8 to 5.5 V * Supply voltage range for on-chip voltage generator VDD2 and VDD3 to VSS1 and VSS2 2.5 to 4.5 V * Display supply voltage range VLCD to VSS: - Normal mode 4 to 9 V - Icon mode 3 to 9 V. * Low power consumption, suitable for battery operated systems * CMOS compatible inputs * Manufactured in silicon gate CMOS process. 5 ORDERING INFORMATION TYPE NUMBER PCF8531U/2 PACKAGE NAME - chip with bumps in tray DESCRIPTION VERSION - 2 APPLICATIONS * Telecommunication systems * Automotive information systems * Point-of-sale terminals * Instrumentation. 3 GENERAL DESCRIPTION
The PCF8531 is a low power CMOS LCD row/column driver, designed to drive dot matrix graphic displays at multiplex rates of 1 : 17, 1 : 26 and 1 : 34. Furthermore, it can drive up to 128 icons. All necessary functions for the display are provided in a single chip, including on-chip generation of VLCD and the LCD bias voltages, resulting in a minimum of external components and low power consumption. The PCF8531 is compatible with most microcontrollers and communicates via a two-line bidirectional bus (I2C-bus). All inputs are CMOS compatible. Remark: The icon mode is used to save current. When only icons are displayed, a much lower operating voltage (VLCD) can be used and the switching frequency of the LCD outputs is reduced. In most applications it is possible to use VDD as VLCD. 4 PACKAGES
The PCF8531 is available as chip with bumps in tray.
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Philips Semiconductors
Product specification
34 x 128 pixel matrix driver
6 BLOCK DIAGRAM
PCF8531
handbook, full pagewidth
R0 to R33
C0 to C127
VDD1
VDD2
VDD3
34 VSS1 VSS2 T1 T2 T3 T4 ROW DRIVERS
128 COLUMN DRIVERS POWER-ON RESET ENR
PCF8531
INTERNAL RESET
RES
DATA LATCHES VLCDIN BIAS VOLTAGE GENERATOR MATRIX LATCHES
OSCILLATOR
OSC
TIMING GENERATOR DISPLAY DATA RAM VLCD GENERATOR MATRIX DATA RAM DISPLAY ADDRESS COUNTER
VLCDSENSE VLCDOUT
SCL SDA SDACK INPUT FILTERS
I2C-BUS CONTROL
COMMAND DECODER
ADDRESS COUNTER
MGS465
SA0
Fig.1 Block diagram.
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Philips Semiconductors
Product specification
34 x 128 pixel matrix driver
7 PINNING SYMBOL OSC VLCDSENSE VLCDOUT VLCDIN RES VDD3 VDD2 VDD1 SDA SDACK SA0 ENR T4 VSS2 VSS1 T3 T1 SCL T2 R0 R2 R4 R6 R8 R10 R12 R14 R16 R18 R20 R22 R24 R26 R28 R30 R32 2000 Feb 11 PAD 1 to 14 15 16 17 to 23 24 to 30 31 32 to 34 35 to 42 43 to 49 50 and 51 52 53 54 55 56 57 to 63 64 to 70 71 72 73 and 74 75 to 77 78 79 to 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 dummy pads oscillator input; note 1 voltage multiplier regulation input (VLCD); note 2 voltage multiplier output (VLCD); note 3 LCD supply voltage (VLCD); note 2 external reset input (active LOW); note 4 supply voltage 3; note 5 supply voltage 2; note 5 supply voltage 1; note 5 serial data line input of the I2C-bus serial data acknowledge output; note 6 dummy pad I2C-bus slave address input; bit 0 enable internal Power-on reset input; note 7 test 4 input; note 8 ground 2; note 9 ground 1; note 9 test 3 input; note 8 test 1 input; note 8 serial clock line input of the I2C-bus dummy pads test 2 output; note 10 dummy pads LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output 5 DESCRIPTION
PCF8531
Philips Semiconductors
Product specification
34 x 128 pixel matrix driver
PCF8531
SYMBOL C0 to C127 R33 R31 R29 R27 R25 R23 R21 R19 R17 R15 R13 R11 R9 R7 R5 R3 R1 Notes
PAD 104 to 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 LCD column driver outputs LCD row driver output; icon row LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output
DESCRIPTION
1. If the on-chip oscillator is used, this input must be connected to VDD1. 2. If the internal VLCD generation is used, VLCDOUT, VLCDIN and VLCDSENSE must be connected together. 3. If an external VLCD is used in the application, then pin VLCDOUT must be left open circuit, otherwise the chip will be damaged. 4. If only the internal Power-on reset is used, this input must be connected to VDD1. 5. VDD1 is for the logic supply, VDD2, and VDD3 are for the voltage multiplier. For split power supplies, VDD2 and VDD3 must be connected together. If only one supply voltage is available, VDD1, VDD2 and VDD3 must be connected together. 6. Serial data acknowledge for the I2C-bus. By connecting SDACK to SDA externally, the SDA line becomes fully I2C-bus compatible. Having the acknowledge output separated from the serial data line is advantageous in Chip-On-Glass (COG) applications. In COG applications where the track resistance from the SDACK pad to the system SDA line can be significant, a potential divider is generated by the bus pull-up resistor and the Indium Tin Oxide (ITO) track resistance. It is possible that the PCF8531 will not be able to create a valid logic 0 level during the acknowledge cycle. By splitting the SDA input from the SDACK output, the device could be used in a mode that ignores the acknowledge bit. In COG applications where the acknowledge cycle is required, it is necessary to minimize the track resistance from the SDACK pad to the system SDA line to guarantee a valid LOW level. 7. If ENR is connected to VSS, Power-on reset is disabled; to enable Power-on reset ENR should be connected to VDD1. 8. In the application, this input must be connected to VSS. 9. VSS1 and VSS2 must be connected together. 10. In the application, T2 must be left open circuit.
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Philips Semiconductors
Product specification
34 x 128 pixel matrix driver
8 8.1 FUNCTIONAL DESCRIPTION Oscillator 8.10 Bias voltage generator
PCF8531
The on-chip oscillator provides the clock signal for the display system. No external components are required and the OSC input must be connected to VDD. An external clock signal, if used, is connected to this input. 8.2 Power-on reset
The bias voltage generator generates four buffered intermediate bias voltages. This block contains the generator for the reference voltages and the four buffers. This block can operate in two voltage ranges: * Normal mode; 4.0 to 9.0 V * Power save mode; 3.0 to 9.0 V.
The on-chip Power-on reset initializes the chip after Power-on or power failure. 8.3 I2C-bus controller
8.11
VLCD generator
The VLCD voltage generator contains a configurable 2 to 5 times voltage multiplier; this is software programmable. 8.12 Reset
The I2C-bus controller receives and executes the commands. The PCF8531 acts as an I2C-bus slave receiver and therefore cannot control bus communication. 8.4 Input filters
To enhance noise immunity in electrically adverse environments, RC low-pass filters are provided on the SDA and SCL lines. 8.5 Display data RAM
The PCF8531 has the possibility of two reset modes, internal Power-on reset or external reset (RES). The reset mode is selected using the ENR signal. After a reset, the chip has the following state: * All row and column outputs are set to VSS (display off) * RAM data is undefined * Power-down mode. 8.13 Power-down
The PCF8531 contains a 34 x 128 bits static RAM, which stores the display data. The RAM is divided into 6 banks of 128 bytes (6 x 8 x 128 bits). Bank 6 is used for icon data. During RAM access, data is transferred to the RAM via the I2C-bus interface. There is a direct correspondence between the X address and column output number. 8.6 Timing generator
During power-down, all static currents are switched off (no internal oscillator, no timing and no LCD segment drive system), and all LCD outputs are internally connected to VSS. The I2C-bus function remains operational. 8.14 Column driver outputs
The timing generator produces the various signals required to drive the internal circuitry. Internal chip operation is not disturbed by operations on the data buses. 8.7 Address counter
The address counter sets the addresses of the display data RAM for writing. 8.8 Display address counter
The LCD drive section includes 128 column outputs (C0 to C127) which should be connected directly to the LCD. The column output signals are generated in accordance with the multiplexed row signals and with the data in the display latch. When less than 128 columns are required, the unused column outputs should be left open circuit. 8.15 Row driver outputs
The display address counter generates the addresses for read out of the display data. 8.9 Command decoder
The command decoder identifies command words that arrive on the I2C-bus and determines the destination for the following data bytes.
The LCD drive section includes 34 row outputs (R0 to R33), which should be connected directly to the LCD. The row output signals are generated in accordance with the selected LCD drive mode. If less than 34 rows or lower Mux rates are required, the unused outputs must be left open circuit. The row signals are interlaced i.e. the selection order is R0, R2, ..., R1, R3 etc.
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Philips Semiconductors
Product specification
34 x 128 pixel matrix driver
8.16 LCD waveforms and DDRAM to data mapping
PCF8531
The LCD waveforms and the DDRAM to display data mapping are shown in Figs 2, 3 and 4.
frame n
VLCD V2 V3 V4 V5 VSS VLCD V2 V3 V4 V5 VSS VLCD V2 V3 V4 V5 VSS VLCD V2 V3 V4 V5 VSS
frame n + 1 Vstate1(t) Vstate2 (t)
ROW 0 R0 (t)
ROW 2 R2 (t)
COL 0 C0 (t)
COL 1 C1 (t)
VLCD V3 - VSS VLCD - V2 0V V3 - V2 V4 - V5 0V VSS - V5 V4 - VLCD -VLCD VLCD V3 - VSS VLCD - V2 0V V3 - V2 V4 - V5 0V VSS - V5 V4 - VLCD -VLCD
Vstate1(t)
Vstate2 (t)
0 2 4 6 8...
... 32 1 3 5 7...
... 33 0 2 4 6 8...
... 32 1 3 5 7...
... 33
MGS466
Vstate1(t) = C1(t) - R0(t). Vstate2(t) = C1(t) - R2(t).
Fig.2 Typical LCD driver waveforms.
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Philips Semiconductors
Product specification
34 x 128 pixel matrix driver
PCF8531
frame n
VLCD V2 V3
frame n + 1 only icons are driven
ROW 0 to 32
V4 V5 VSS
VLCD V2 V3
ROW 33
V4 V5 VSS VLCD V2 V3
COL 1 on/off
V4 V5 VSS VLCD V2 V3
COL 2 off/on
V4 V5 VSS
VLCD V2 V3
COL 3 on/on
V4 V5 VSS VLCD V2 V3
COL 4 off/off
V4 V5 VSS
MGS467
Fig.3 Icon mode; Mux 1 : 2 LCD waveforms.
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Philips Semiconductors
Product specification
34 x 128 pixel matrix driver
PCF8531
DDRAM
bank 0 top of LCD R0
bank 1
R8
bank 2
R16
LCD
bank 3
R24
bank 4
R32 R33 (icon row)
bank 5
MGS468
Fig.4 DDRAM to display mapping.
2000 Feb 11
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Philips Semiconductors
Product specification
34 x 128 pixel matrix driver
8.17 Addressing
PCF8531
column. In horizontal addressing mode (V = 0), the X address increments after each byte (see Fig.7). After the last X address (X = 127), X wraps around to 0 and Y increments to address the next row. After the very last address (X = 127 and Y = 4), the address pointers wrap around to address (X = 0 and Y = 0). It should be noted that in bank 4 only the LSB (DB0) of the data will be written into the RAM. The Y address 5 is reserved for icon data and is not affected by the addressing mode; it should be noted that in bank 5 only the 5th data bit (DB4) will be written into the RAM.
Data is written in bytes into the RAM matrix of the PCF8531 as illustrated in Figs 5, 6 and 7. The display RAM has a matrix of 34 x 128 bits. The columns are addressed by the address pointer. The address ranges are X 0 to X 127 (7FH) and Y 0 to Y 5 (5H). Addresses outside of these ranges are not allowed. In vertical addressing mode (V = 1), the Y address increments after each byte (see Fig.6). After the last Y address (Y = 4), Y wraps around to 0 and X increments to address the next
LSB handbook, full pagewidth
0 MSB LSB 1 2 Y address 3 MSB LSB icon data 0 MSB X address 127 4 5
MGS469
Fig.5 RAM format and addressing.
handbook, full pagewidth
0 1 2 3 4 0
5 6
638 639 1 icon data
0 1 2 Y address 3 4 5
0
X address
127
MGS470
Fig.6 Sequence of writing data bytes into RAM with vertical addressing (V = 1).
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Philips Semiconductors
Product specification
34 x 128 pixel matrix driver
PCF8531
handbook, full pagewidth
0 128 256 384 512 0
1 129 257 385 513 1
2 130 258 386 514 icon data
127 255 383 511 639
0 1 2 3 4 5 Y address
0
X address
127
MGS471
Fig.7 Sequence of writing data bytes into RAM with horizontal addressing (V = 0).
8.18
Instructions
8.18.1
RESET
Only two PCF8531 registers, the Instruction Register (IR) and the Data Register (DR) can be directly controlled by the MPU. Before internal operation, control information is stored temporarily in these registers to allow interfacing to various types of MPUs which operate at different speeds or to allow interfacing to peripheral control ICs. The PCF8531 operation is controlled by the instructions given in Table 1. Details are explained in subsequent sections. Instructions are of four types: 1. Those that define PCF8531 functions such as display configuration, etc. 2. Those that set internal RAM addresses 3. Those that perform data transfer with internal RAM 4. Others. In normal use, category 3 instructions are used most frequently. Automatic incrementing by 1 of internal RAM addresses after each data write reduces the MPU program load.
After reset or internal Power-on reset (depending on application), the LCD driver will be set to the following state: * Power-down mode (PD = 1) * Horizontal addressing (V = 0) * Display blank (D = 0; E = 0), no icon mode (IM = 0) * Address counter X[6:0] = 0; Y[2:0] = 0 * Bias system BS[2:0] = 0 * Multiplex rate M[1:0] = 0 (Mux rate 1 : 17) * Temperature control mode TC[2:0] = 0 * HV-gen control, HVE = 0 the HV generator is switched off, PRS = 0 and S[1:0] = 0 * VLCD = 0 V * RAM data is undefined * Command page definition H[1:0] = 0.
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Philips Semiconductors
Product specification
34 x 128 pixel matrix driver
8.18.2 FUNCTION SET 8.18.4 SET X ADDRESS
PCF8531
8.18.2.1
PD
When PD = 1, the Power-down mode of the LCD driver is active: * All LCD outputs at VSS (display off) * Power-on reset detection active, oscillator off * VLCD can be disconnected * I2C-bus is operational, commands can be executed * RAM contents not cleared; RAM data can be written * Register settings remain unchanged.
The X address points to the columns. The range of X is 0 to 127 (7FH). 8.18.5 SET MULTIPLEX RATE
M[1:0] selects the multiplex rate (see Table 8). 8.18.6 DISPLAY CONTROL (D, E AND IM)
Bits D and E select the display mode (see Table 6). Bit IM sets the display to icon mode. 8.18.7 SET BIAS SYSTEM
8.18.2.2
V
When V = 0 the horizontal addressing is selected. The data is written into the DDRAM as shown in Fig.7. When V = 1 the vertical addressing is selected. The data is written into the DDRAM as shown in Fig.6. Icon data is written independently of V when Y address is 5. 8.18.3 SET Y ADDRESS
Different multiplex rates require different bias settings. These are programmed by BS[2:0], which sets the binary number n. The optimum value for n is given by n= Mux rate - 3
Supported values of n are given in Table 2. Table 3 shows the intermediate bias voltages.
Bits Y2, Y1 and Y0 define the Y address vector of the display RAM. Table 1 Y2 0 0 0 0 1 1 Table 2 Y address Y1 0 0 1 1 0 0 Y0 0 1 0 1 0 1 BANK 0 1 2 3 4 5 (icons)
Programming the required bias system BS[1] 0 0 1 1 0 0 1 1 BS[0] 0 1 0 1 0 1 0 1 n 7 6 5 4 3 2 1 0 BIAS SYSTEM
1 1 11
BS[2] 0 0 0 0 1 1 1 1
COMMENT
10 1 9 1 8 1 7 1 6 1 5 1 4
recommended for 1 : 34 recommended for 1 : 26 recommended for 1 : 17 recommended for icon mode
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Philips Semiconductors
Product specification
34 x 128 pixel matrix driver
8.18.8 Table 3 LCD BIAS VOLTAGE Intermediate LCD bias voltages BIAS VOLTAGES VLCD n+3 ------------ x V LCD n+4 n+2 ------------ x V LCD n+4 2 ------------ x V LCD n+4 1 ------------ x V LCD n+4 VSS SET VOP VALUE: EXAMPLE FOR 1 BIAS 7 VLCD
6 7
PCF8531
The generated voltage is dependent on the temperature, programmed Temperature Coefficient (TC) and the programmed voltage at reference temperature (Tcut). VLCD = VLCD (Tcut) x [1 + TC x (T - Tcut)]. The parameter values are given in Table 4. Two overlapping VLCD ranges can be selected via the command `HV-gen control' (see Table 4 and Fig.8). The maximum voltage that can be generated depends on the VDD2 and VDD3 voltages and the display load current. For Mux 1 : 34, the optimum operating voltage of the liquid can be calculated as: 1 + 34 V LCD = -------------------------------------- x V th = 5.30 x V th 1 1 - ---------- 2x 34 Where Vth is the threshold voltage of the liquid crystal material used. The practical value for VOP is determined by equating Voff(rms) with a defined LCD threshold voltage (Vth), typically when the LCD exhibits approximately 10% contrast. As the programming range for the internally generated VLCD allows values above the maximum allowed VLCD, the user has to ensure, while setting the VOP register and selecting the temperature compensation, that the VLCD limit of maximum 9 V will never be exceeded under all conditions and including all tolerances.
SYMBOL V1 V2
x VLCD
V3
5
7
x VLCD
V4
2
7
x VLCD
V5
1
7
x VLCD
V6 8.18.9
VSS
The operating voltage VLCD can be set by software. The voltage at reference temperature [VLCD (T = Tcut)] can be calculated as: VLCD (Tcut) = (a + VOP x b).
Table 4
Parameter values for the HV generator programming VALUE SYMBOL PRS = 0 PRS = 1 27 6.75 0.03 6.75 to 10.56 C V V V UNIT 27 2.94 0.03 2.94 to 6.75
Tcut a b Programming range
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Philips Semiconductors
Product specification
34 x 128 pixel matrix driver
PCF8531
handbook, full pagewidth
VLCD
b
a
00
01
02
03
04
05 LOW
06
. . . 7D 7E
7F
00
01
02
03
04
05 HIGH
06
. . . 5F
6F
7F
MGL935
VOP[6:0] (programmed) [00H to 7FH] programme range LOW and HIGH.
Fig.8 VOP programming of PCF8531.
8.18.10 VOLTAGE MULTIPLIER CONTROL S[1:0] The PCF8531 incorporates a software configurable voltage multiplier. After reset (internal or external), the voltage multiplier is set to 2 x VDD2. The voltage multiplier factors are set via the command `HV-gen configuration' (see Tables 4, 5 and 6). 8.18.11 TEMPERATURE COMPENSATION Due to the temperature dependency of the liquid crystal's viscosity, the LCD controlling voltage VLCD should usually be increased at lower temperatures to maintain optimum contrast. Figure 9 shows VLCD for high multiplex rates. Linear temperature compensation is supported in the PCF8531. The temperature coefficient of VLCD can be selected from eight values by setting bits TC[2:0] (see Tables 4, 5 and 6). Fig.9
0 C T
handbook, halfpage
MGS473
VLCD
VLCD as a function of liquid crystal temperature.
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Philips Semiconductors
Product specification
34 x 128 pixel matrix driver
Table 5 Instruction set I2C-BUS COMMAND(1) RS R/W I2C-BUS COMMAND BYTE
PCF8531
INSTRUCTION
DESCRIPTION DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
H1 and H0 = don't care (H independent command page) NOP Write data Set default H[1:0] 0 1 0 0 0 0 0 D7 0 0 D6 0 0 D5 0 0 D4 0 0 D3 0 0 D2 0 0 D1 0 0 D0 1 no operation write data to display RAM select H[1:0] = 0
H1 = 0 and H0 = 0 (function and RAM command page) Instruction set Function set Set Y address of RAM Set X address of RAM 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 X6 0 1 0 X5 0 0 0 X4 1 0 0 X3 0 PD Y2 X2 H1 V Y1 X1 H0 0 Y0 X0 select command page power-down control; entry mode set Y address of RAM; 0Y5 set X address part of RAM; 0 X 127
H1 = 0 and H0 = 1 (display setting command page) Multiplex rate Display control Bias system 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 D BS2 M1 IM BS1 M0 E select multiplex rate set display configuration
BS0 set Bias System (BSx)
H1 = 1 and H0 = 0 (HV-gen command page) HV-gen control HV-gen configuration Temperature control Test modes VLCD control Note 1. R/W is set in the slave address byte; Co and RS are set in the control byte. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 X 0 0 0 X 0 1 0 X 1 0 TC2 X PRS HVE set VLCD programming range S1 TC1 X S0 set voltage multiplication factor
TC0 set temperature coefficient X do not use (reserved for test)
VOP6 VOP5 VOP4 VOP3 VOP2 VOP1 VOP0 set VLCD register 0 VOP 127
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Philips Semiconductors
Product specification
34 x 128 pixel matrix driver
Table 6 Explanations for symbols in Table 5 BIT PD V IM H[1:0](1) D and E HVE PRS TC[2:0] S[1:0] Note 1. The H-bits identify the command page (use set default H[1:0] command to set H[1:0] = 0. Table 7 BITS Description of bits H, D and E, TC and S VALUE DESCRIPTION Table 8 Multiplex rates M1 0 1 0 chip is active horizontal addressing normal mode; full display + icons see Table 7 see Table 7 voltage multiplier disabled VLCD programming range LOW see Table 7 see Table 7 0 1
PCF8531
chip is in Power-down mode vertical addressing icon mode; only icons are displayed
voltage multiplier enabled VLCD programming range HIGH
MUX RATE 1 : 17 1 : 26 1 : 34
M0 0 0 1
Command page (H) H[1:0] 00 01 10 function and RAM command page display setting command page HV-gen command page
Display modes (D, E) D and E 00 10 01 11 display blank normal mode all display segments inverse video mode
Temperature coefficient (TC) TC[2:0] 000 001 010 011 100 101 110 111 temperature coefficient 0 temperature coefficient 1 temperature coefficient 2 temperature coefficient 3 temperature coefficient 4 temperature coefficient 5 temperature coefficient 6 temperature coefficient 7 2 x voltage multiplier 3 x voltage multiplier 4 x voltage multiplier 5 x voltage multiplier
Voltage multiplier factor (S) S[1:0] 00 01 10 11
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Philips Semiconductors
Product specification
34 x 128 pixel matrix driver
9 9.1 I2C-BUS INTERFACE Characteristics of the I2C-bus
PCF8531
* Slave: the device addressed by a master * Multi-Master: more than one master can attempt to control the bus at the same time without corrupting the message * Arbitration: procedure to ensure that, if more than one master simultaneously tries to control the bus, only one is allowed to do so and the message is not corrupted * Synchronization: procedure to synchronize the clock signals of two or more devices. 9.1.4 ACKNOWLEDGE
The I2C-bus is for bi-directional, two-line communication between different ICs or modules. The two lines are a Serial Data line (SDA) and a Serial Clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only when the bus is not busy. 9.1.1 BIT TRANSFER
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as a control signal (see Fig.10). 9.1.2 START AND STOP CONDITIONS
Acknowledge on the I2C-bus is illustrated in Fig.13. Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH signal put on the bus by the transmitter, during which time the master generates an extra acknowledge related clock pulse. A slave receiver that is addressed must generate an acknowledge after the reception of each byte. Also, a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse so that the SDA line is stable LOW during the HIGH period of the acknowledge- related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an "end of data" to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition.
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P). The START and STOP conditions are illustrated in Fig.11. 9.1.3 SYSTEM CONFIGURATION
The system configuration is illustrated in Fig.12 * Transmitter: the device that sends the data to the bus * Receiver: the device that receives the data from the bus * Master: the device that initiates a transfer, generates clock signals and terminates a transfer
handbook, full pagewidth
SDA
SCL data line stable; data valid change of data allowed
MBC621
Fig.10 Bit transfer.
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Philips Semiconductors
Product specification
34 x 128 pixel matrix driver
PCF8531
handbook, full pagewidth
SDA
SDA
SCL S START condition P STOP condition
SCL
MBC622
Fig.11 Definition of START and STOP conditions.
MASTER TRANSMITTER/ RECEIVER SDA SCL
SLAVE RECEIVER
SLAVE TRANSMITTER/ RECEIVER
MASTER TRANSMITTER
MASTER TRANSMITTER/ RECEIVER
MGA807
Fig.12 System configuration.
handbook, full pagewidth
DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER S START condition clock pulse for acknowledgement
MBC602
1
2
8
9
Fig.13 Acknowledge on the I2C-bus.
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Philips Semiconductors
Product specification
34 x 128 pixel matrix driver
9.2 I2C-bus protocol
PCF8531
The data pointer is automatically updated and the data is directed to the intended PCF8531 device. If the RS bit of the last control byte was set to logic 0, these command bytes will be decoded and the setting of the device will be changed according to the received commands. The acknowledgement after each byte is made only by the addressed PCF8531. At the end of the transmission, the I2C-bus master issues a STOP condition (P). 9.3 Command decoder
This driver does not support `read'. The PCF8531 is a slave receiver. Therefore, it only responds when R/W = 0 in the slave address byte. Before any data is transmitted on the I2C-bus, the device that should respond is addressed first. Two 7-bit slave addresses (0111100 and 0111101) are reserved for the PCF8531. The least significant bit of the slave address is set by connecting the input SA0 to either logic 0 (VSS) or logic 1 (VDD). The I2C-bus protocol is illustrated in Fig.14. The sequence is initiated with a START condition (S) from the I2C-bus master, and is followed by the slave address. All slaves with the corresponding address acknowledge in parallel, all others ignore the I2C-bus transfer. After acknowledgement, one or more command words follow, which define the status of the addressed slaves. A command word consists of a control byte, which defines Co and RS, plus a data byte (see Fig.14 and Table 1). The last control byte is tagged with a cleared most significant bit, the continuation bit Co. The control and data bytes are also acknowledged by all addressed slaves on the bus. After the last control byte, depending on the RS bit setting, either a series of display data bytes or command data bytes may follow. If the RS bit was set to logic 1, these display bytes are stored in the display RAM at the address specified by the data pointer.
* Pairs of bytes; information in the second byte, the first byte determines whether information is display or instruction data * Stream of information bytes after Co = 0; display or instruction data, depending on last RS (Register Selection). The command decoder identifies command words that arrive on the I2C-bus. The most significant bit of a control byte is the continuation bit Co. If this bit is logic 1, it indicates that only one data byte (either command or RAM data) will follow. If this bit is logic 0, it indicates that a series of data bytes (either command or RAM data) may follow. The DB6 bit of a control byte is the RAM data/command bit RS. When this bit is at logic 1, it indicates that another RAM data byte will be transferred next. If the bit is at logic 0, it indicates that another command byte will be transferred next.
handbook, full pagewidth
slave address S 0 1 1 1 1 0 SA0 R/W A Co RS X
control byte X X X X X
MGS474
Fig.14 Slave address and control byte.
2000 Feb 11
20
Philips Semiconductors
Product specification
34 x 128 pixel matrix driver
PCF8531
handbook, full pagewidth
acknowledge from PCF8531
acknowledge from PCF8531
acknowledge from PCF8531
acknowledge from PCF8531
acknowledge from PCF8531
S S 0 1 1 1 1 0 A 0 A 1 RS 0 slave address
control byte
A
data byte
A 0 RS
control byte
A
data byte
AP
R/W Co
2n 0 bytes
Co
1 byte
n 0 bytes MSB . . . . . . . . . . . LSB
MGS475
Fig.15 Master transmits to slave receiver; write mode.
10 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134); note 1. SYMBOL VDD1 VDD2, VDD3 IDD VLCD ILCD ISS VI/VO II IO Ptot P/out Tstg Tj Note 1. Parameters are valid over the operating temperature range unless otherwise specified. All voltages referenced to VSS unless otherwise noted. 11 HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is recommended to take normal precautions appropriate to handling MOS devices (see "Handling MOS Devices"). logic supply voltage multiplier supply voltage supply current LCD supply voltage LCD supply current negative supply current input/output voltage (any input/output) DC input current DC output current total power dissipation per package power dissipation per output storage temperature junction temperature PARAMETER MIN. -0.5 -0.5 -50 -0.5 -50 -50 -0.5 -10 -10 - - -65 - MAX. +5.5 +4.5 +50 +9.0 +50 +50 VDD + 0.5 +10 +10 300 30 +150 150 V V mA V mA mA V mA mA mW mW C C UNIT
2000 Feb 11
21
Philips Semiconductors
Product specification
34 x 128 pixel matrix driver
12 DC CHARACTERISTICS VDD1 = 1.8 (1.9) to 5.5 V; VDD2 and VDD3 = 2.5 to 4.5 V; VSS1,2 = 0 V; VDD1 to VDD3 VLCD 9.0 V; Tamb = -40 to +85 C; unless otherwise specified. SYMBOL Supplies VLCD VDD1 VDD2, VDD3 IDD LCD supply voltage logic supply voltage Tamb -25 C multiplier supply voltage supply current LCD voltage internally generated Power-down mode; internal VLCD normal mode; internal VLCD; notes 2 and 3 normal mode; external VLCD; note 2 ILCD LCD input current normal mode; external VLCD; notes 2 and 4 icon mode; external VLCD; notes 2 and 5 VPOR Logic VIL VIH IOL ILI Ro(col) Ro(row) Vbias(col) Vbias(row) LOW-level input voltage HIGH-level input voltage LOW-level output current (SDA) input leakage current VOL = 0.4 V; VDD = 5 V VI = VDD or VSS note 7 note 7 VSS 3.0 -1 - - -100 -100 - - - 12 12 0 0 Power-on reset level note 6 note 1 icon mode; note 1 4.0 3.0 1.9 1.8 2.5 - - - - - 0.9 - - - - - 2 170 10 25 15 1.2 PARAMETER CONDITIONS MIN. TYP.
PCF8531
MAX.
UNIT
9.0 9.0 5.5 5.5 4.5 10 350 50 100 70 1.6
V V V V V A A A A A V
0.3VDD V VDD - +1 V mA A k k mV mV
0.7VDD -
Column and row outputs column output resistance C0 to C127 row output resistance R0 to R33 bias tolerance C0 to C127 bias tolerance R0 to R33 20 20 +100 +100
2000 Feb 11
22
Philips Semiconductors
Product specification
34 x 128 pixel matrix driver
PCF8531
SYMBOL VLCD generation VLCD(tol) TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7 Tcut Notes
PARAMETER
CONDITIONS - - - - - - - - - -
MIN. - 0
TYP.
MAX. 3.9 -
UNIT
LCD voltage tolerance, internal VLCD LCD voltage temperature coefficient 0 LCD voltage temperature coefficient 1 LCD voltage temperature coefficient 2 LCD voltage temperature coefficient 3 LCD voltage temperature coefficient 4 LCD voltage temperature coefficient 5 LCD voltage temperature coefficient 6 LCD voltage temperature coefficient 7 cut point temperature
TC1 to TC7; note 8 Tamb = -20 to +70 C Tamb = -20 to +70 C Tamb = -20 to +70 C Tamb = -20 to +70 C Tamb = -20 to +70 C Tamb = -20 to +70 C Tamb = -20 to +70 C Tamb = -20 to +70 C
% %/C %/C %/C %/C %/C %/C %/C %/C C
-0.026 - -0.039 - -0.052 - -0.078 - -0.13 -0.19 -0.26 27 - - - -
1. As the programming range for the internally generated VLCD allows values above the maximum allowed VLCD, the user has to ensure, while setting the VOP register and selecting the temperature compensation, that the VLCD limit of maximum 9 V will never be exceeded under all conditions and including all tolerances. 2. LCD outputs are open circuit, inputs at VDD or VSS; bus inactive. 3. VDD1 to VDD3 = 2.85 V; VLCD = 7.0 V; voltage multiplier = 3 x VDD; fOSC = 34 kHz. 4. VDD1 to VDD3 = 2.75 V; VLCD = 9.0 V; fOSC = 34 kHz. 5. VDD1 to VDD3 = 2.75 V; VLCD = 3.5 V; fOSC = 34 kHz. 6. Resets all logic when VDD1 < VPOR. 7. ILOAD 50 A; outputs tested one at a time. 8. VLCD 7.7 V.
2000 Feb 11
23
Philips Semiconductors
Product specification
34 x 128 pixel matrix driver
13 AC CHARACTERISTICS VDD1 = 1.8 to 5.5 V; VDD2 and VDD3 = 2.5 to 4.5 V; VSS1 and VSS2 = 0 V; VDD1 to VDD3 VLCD 9.0 V; Tamb = -40 to +85 C; unless otherwise specified. SYMBOL fframe fOSC fclk(ext) tW(RESL) tSU;RESL fSCL tSCLL tSCLH tSU;DAT tHD;DAT tr tf Cb tSU;STA tHD;STA tSU;STO tSW tBUF Notes 1. fframe = fclk(ext)/480; fOSC/480. 2. For tW(RESL) > 3 ns a reset may be generated. PARAMETER LCD frame frequency (internal clock) oscillator frequency (not available at any pin) external clock frequency reset LOW pulse width reset LOW pulse set-up time after Power-on note 2 CONDITIONS VDD = 3.0 V; note 1 40 20 20 300 - 0 1.3 0.6 100 0 note 4 note 4 20 + 0.1Cb 20 + 0.1Cb - 0.6 0.6 0.6 - 1.3 MIN. TYP. 66 34 - - - - - - - - - - - - - - - -
PCF8531
MAX. 135 65 65 - 30
UNIT Hz kHz kHz ns s kHz s s ns s ns ns pF s s s ns s
Serial-bus interface; note 3 SCL clock frequency SCL clock LOW period SCL clock HIGH period data set-up time data hold time SCL, SDA rise time SCL, SDA fall time capacitive load represented by each bus line set-up time for a repeated START condition start condition hold time set-up time for STOP condition tolerable spike width on bus bus free time between a STOP and START condition 400 - - - 0.9 300 300 400 - - - 50 -
3. All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an input voltage swing of VSS to VDD. 4. Cb = total capacitance of one bus line in pF.
handbook, full pagewidth
VDD
RES VIL t SU; RESL t W(RESL)
MGS476
Fig.16 Reset timing.
2000 Feb 11
24
Philips Semiconductors
Product specification
34 x 128 pixel matrix driver
PCF8531
ndbook, full pagewidth
SDA
t BUF
t LOW
tf
SCL
t HD;STA
tr
t HD;DAT
t HIGH
t SU;DAT
SDA t SU;STA
MGA728
t SU;STO
Fig.17 I2C-bus timing diagram.
MGS477
handbook, halfpage
400
MGS478
handbook, halfpage
400
IDD (A) 300
IDD (A) 300
2x 5x 4x 3x
VLCD = 9 V 200 7.5 V 4V
200
100 2 3 4 5 VDD2 and VDD3 (V)
100
2
4
6
8 VLCD (V)
10
VDD1 = 2 V; 4 x voltage multiplier; Tamb = 27 C; TC = 0; BS = 100; no VLCD load.
VDD1 = 1.8 V; VDD2 and VDD3 = 2.6 V; Tamb = 27 C; fOSC = 34 kHz; no VLCD load.
Fig.18 IDD, internal VLCD generation.
Fig.19 IDD for different multiplication factors.
2000 Feb 11
25
Philips Semiconductors
Product specification
34 x 128 pixel matrix driver
PCF8531
handbook, halfpage
9
MGS479
MGS480
handbook, halfpage
30
VLCD (V) 8 TC0 TC1 7 TC6 TC7
I (A) 20 ILCD
10 IDD
6 -50
0 0 50 T (C) 100 2 4 6 8 VLCD (V) 10
VLCD = 7.5 V; VDD1 to VDD3 = 2.7 V; Tamb = 27 C; no VLCD load.
VDD1 = 1.8 V; VDD2 and VDD3 = 2.5 V; external VLCD; Tamb = 27 C; TC = 0; BS = 100; no VLCD load.
Fig.20 Temperature coefficient.
Fig.21 IDD and ILCD with external VLCD.
MGS481
handbook, halfpage
30
handbook, halfpage
86
MGS482
I (A) I LCD 20
I DD (A) 84
82
10
I DD 80
0 0 20 40 60 f (kHz) 80
78 3 3.2 3.4 3.6 3.8 4 VLCD (V)
VDD1 = 2.5 V; VDD2 and VDD3 = 2.5 V; external VLCD; Tamb = 27 C; TC = 0; BS = 100; no VLCD load.
VDD1 = 1.8 V; VDD1 = 2.5 V; 2 x voltage multiplier; Tamb = 27 C; TC = 0; BS = 111; no VLCD load.
Fig.22 IDD and ILCD dependent from frequency.
Fig.23 Internal VLCD, icon mode.
2000 Feb 11
26
Philips Semiconductors
Product specification
34 x 128 pixel matrix driver
14 APPLICATION INFORMATION Table 9 STEP DB7 1 2 3 0 1 0 DB6 1 0 0 DB5 1 0 0 DB4 1 0 0 DB3 1 0 0 DB2 0 0 0 DB1 SA0 0 0 DB0 0 0 1 Programming example for PCF8531 SERIAL BUS BYTE DISPLAY
PCF8531
OPERATION start; slave address; R/W = 0 control byte; Co = 1; RS = 0 H[1:0] independent command; select function and RAM command page (H[1:0] = 00) control byte; Co = 1; RS = 0 function and RAM command page PD = 0 and V = 1 control byte; Co = 1; RS = 0 function and RAM command page select display setting command page H[1:0] = 01 control byte; Co = 1; RS = 0 display setting command page; set normal mode (D = 1; IM = 0 and E = 0) control byte; Co = 1; RS = 0 select Mux rate 1 : 34 control byte; Co = 1; RS = 0 H[2:0] independent command; select function and RAM command page H[1:0] = 00 control byte; Co = 1; RS = 0 function and RAM command page; select HV-gen command page H[1:0] = 10 control byte; Co = 1; RS = 0 HV-gen command page; select voltage multiplication factor 5 S[1:0] = 11 control byte; Co = 1; RS = 0 HV-gen command page; select temperature coefficient 2 TC[2:0] = 010 control byte; Co = 1; RS = 0
4 5 6 7
1 0 1 0
0 0 0 0
0 1 0 0
0 0 0 0
0 0 0 1
0 0 0 0
0 1 0 0
0 0 0 1
8 9
1 0
0 0
0 0
0 0
0 1
0 1
0 0
0 0
10 11 12 13
1 0 1 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 1 0 0
0 0 0 0
0 1 0 1
14 15
1 0
0 0
0 0
0 0
0 1
0 0
0 1
0 0
16 17
1 0
0 0
0 0
0 0
0 1
0 0
0 1
0 1
18 19
1 0
0 0
0 1
0 0
0 0
0 0
0 1
0 0
20
1
0
0
0
0
0
0
0
2000 Feb 11
27
Philips Semiconductors
Product specification
34 x 128 pixel matrix driver
PCF8531
SERIAL BUS BYTE STEP DB7 21 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 1 DB1 1 DB0 1 HV-gen command page; select high VLCD programming range (PRS = 1); voltage multiplier off (HVE = 1) control byte; Co = 1; RS = 0 HV-gen command page; set VLCD = 7.71 V; VOP[6:0] = 0100000 control byte; Co = 0; RS = 1 data write; Y and X are initialized to 0 by default, so they are not set here
MGS405
DISPLAY
OPERATION
22 23
1 1
0 0
0 1
0 0
0 0
0 0
0 0
0 0
24 25
0 0
1 0
0 0
0 1
0 1
0 1
0 1
0 1
26
0
0
0
0
0
1
0
1
data write
MGS406
27
0
0
0
0
0
1
1
1
data write
MGS407
28
0
0
0
0
0
0
0
0
data write
MGS407
29
0
0
0
1
1
1
1
1
data write
MGS409
30
0
0
0
0
0
1
0
0
data write
MGS410
2000 Feb 11
28
Philips Semiconductors
Product specification
34 x 128 pixel matrix driver
PCF8531
SERIAL BUS BYTE STEP DB7 31 0 DB6 0 DB5 0 DB4 1 DB3 1 DB2 1 DB1 1 DB0 1 data write; last data and stop transmission DISPLAY OPERATION
MGS411
32
0
1
1
1
1
0
SA0
0
repeated start; slave address; R/W = 0
MGS411
33
1
0
0
0
0
0
0
0
control byte; Co = 1; RS = 0
MGS411
34
0
0
0
0
0
0
0
1
H[1:0] independent command; select function and RAM command page H[1:0] = 00
MGS411
35
1
0
0
0
0
0
0
0
control byte; Co = 1; RS = 0
MGS411
36
0
0
0
0
1
0
0
1
function and RAM command page; select display setting command page H[1:0] = 01
MGS411
37
1
0
0
0
0
0
0
0
control byte; Co = 1; RS = 0
MGS411
38
0
0
0
0
0
0
0
1
H[1:0] independent command; select function and RAM command page H[1:0] = 00
MGS411
2000 Feb 11
29
Philips Semiconductors
Product specification
34 x 128 pixel matrix driver
PCF8531
SERIAL BUS BYTE STEP DB7 39 1 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 0 DB0 0 control byte; Co = 1; RS = 0 DISPLAY OPERATION
MGS411
40
0
0
0
0
1
1
0
1
display control; set inverse video mode (D = 1; E = 1 and IM = 0)
MGS412
41
1
0
0
0
0
0
0
0
control byte; Co = 1; RS = 0
MGS412
42
1
0
0
0
0
0
0
0
set X address of RAM; set address to `0000000'
MGS412
43
0
1
0
0
0
0
0
0
control byte; Co = 0; RS = 1
MGS412
44
0
0
0
0
0
0
0
0
data write
MGS414
The pinning of the PCF8531 is optimized for single plane wiring e.g. for chip-on-glass display modules. Display size: 34 x 128 pixels.
2000 Feb 11
30
Philips Semiconductors
Product specification
34 x 128 pixel matrix driver
PCF8531
handbook, full pagewidth
VLCD
VDD1 to VDD3 VDD(I2C) 128 column drivers 34 row drivers Rpu Rpu HOST MICROPROCESSOR/ MICROCONTROLLER SDA
PCF8531
SDACK
LCD PANEL
VSS RES SCL SDA VSS1, VSS2
VSS1, VSS2
ENR
SCL
SA0
RES
MGS483
Fig.24 Typical system configuration.
The host microprocessor/microcontroller and the PCF8531 are both connected to the I2C-bus. The SDA and SCL lines must be connected to the positive power supply via pull-up resistors. The internal oscillator requires no external components. The appropriate intermediate biasing voltage for the multiplexed LCD waveforms are generated on-chip. The only other connections required to complete the system are to the power supplies (VDD, VSS and VLCD) and suitable capacitors for decoupling VLCD and VDD.
2000 Feb 11
31
Philips Semiconductors
Product specification
34 x 128 pixel matrix driver
PCF8531
handbook, full pagewidth
DISPLAY 34 x 128 PIXELS
17
128
17
PCF8531
R I/O
Rsupply
3 VSS1 I/O VDD1 to VDD3 VSS2
Cext
VLCD
MGS484
Fig.25 Chip-on-glass application.
The required minimum values for the external capacitors in an application with the PCF8531 are as follows: * Cext = 100 nF for VLCD and VSS1 and VSS2, and Cext = 470 nF for VDD1 to VDD3 and VSS1 and VSS2 * Higher capacitor values are recommended for ripple reduction * For COG applications, the recommended ITO track resistance is to be minimized for the I/O and supply connections. Optimized values for these tracks are below 50 for the supply (Rsupply) and below 100 for the I/O connections (RI/O). * To reduce the sensitivity of the reset to ESD/EMC disturbances for a chip-on-glass application, it is strongly recommended to implement a series input resistance in the reset line (recommended minimum value 8 k) on the glass (ITO). If the reset input is not used, it should be connected to VDD1 using a short connection.
2000 Feb 11
32
Philips Semiconductors
Product specification
34 x 128 pixel matrix driver
15 BONDING PAD LOCATIONS Table 10 Bonding pad locations All x and y coordinates are referenced to the centre of the chip (dimensions in m; see Fig.28). SYMBOL dummy dummy dummy dummy dummy dummy dummy dummy dummy dummy dummy dummy dummy dummy OSC VLCDSENSE VLCDOUT VLCDOUT VLCDOUT VLCDOUT VLCDOUT VLCDOUT VLCDOUT VLCDIN VLCDIN VLCDIN VLCDIN VLCDIN VLCDIN VLCDIN RES VDD3 VDD3 VDD3 VDD2 VDD2 VDD2 2000 Feb 11 PAD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 x +5973.6 +5969.5 +5899.5 +5829.5 +5479.5 +5409.5 +5059.5 +4989.5 +4639.5 +4569.5 +4219.5 +4149.5 +3799.5 +3729.5 +3449.5 +3169.5 +3099.5 +3029.5 +2959.5 +2889.5 +2819.5 +2749.5 +2679.5 +2539.5 +2469.5 +2399.5 +2329.5 +2259.5 +2189.5 +2119.5 +1979.5 +1699.5 +1629.5 +1559.5 +1279.5 +1209.5 +1139.5 y -821.7 +823.4 +823.4 +823.4 +823.4 +823.4 +823.4 +823.4 +823.4 +823.4 +823.4 +823.4 +823.4 +823.4 +823.4 +823.4 +823.4 +823.4 +823.4 +823.4 +823.4 +823.4 +823.4 +823.4 +823.4 +823.4 +823.4 +823.4 +823.4 +823.4 +823.4 +823.4 +823.4 +823.4 +823.4 +823.4 +823.4 33
PCF8531
SYMBOL VDD2 VDD2 VDD2 VDD2 VDD2 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 SDA SDA SDACK dummy SA0 ENR T4 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 T3 T1 SCL SCL dummy dummy dummy T2
PAD 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78
x +1069.5 +999.5 +929.5 +859.5 +789.5 +649.5 +579.5 +509.5 +439.5 +369.5 +299.5 +229.5 +19.5 -50.5 -400.5 -750.5 -820.5 -1100.5 -1380.5 -1660.5 -1730.5 -1800.5 -1870.5 -1940.5 -2010.5 -2080.5 -2220.5 -2290.5 -2360.5 -2430.5 -2500.5 -2570.5 -2640.5 -2780.5 -3060.5 -3410.5 -3480.5 -3830.5 -4180.5 -4530.5 -4600.5
y +823.4 +823.4 +823.4 +823.4 +823.4 +823.4 +823.4 +823.4 +823.4 +823.4 +823.4 +823.4 +823.4 +823.4 +823.4 +823.4 +823.4 +823.4 +823.4 +823.4 +823.4 +823.4 +823.4 +823.4 +823.4 +823.4 +823.4 +823.4 +823.4 +823.4 +823.4 +823.4 +823.4 +823.4 +823.4 +823.4 +823.4 +823.4 +823.4 +823.4 +823.4
Philips Semiconductors
Product specification
34 x 128 pixel matrix driver
PCF8531
SYMBOL dummy dummy dummy dummy dummy dummy dummy dummy R0 R2 R4 R6 R8 R10 R12 R14 R16 R18 R20 R22 R24 R26 R28 R30 R32 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 2000 Feb 11
PAD 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119
x -4880.5 -4950.5 -5230.5 -5300.5 -5650.5 -5720.5 -5930.5 -5926.4 -5786.4 -5716.4 -5646.4 -5576.4 -5506.4 -5436.4 -5366.4 -5296.4 -5226.4 -5156.4 -5086.4 -5016.4 -4946.4 -4876.4 -4806.4 -4736.4 -4666.4 -4526.4 -4456.4 -4386.4 -4316.4 -4246.4 -4176.4 -4106.4 -4036.4 -3966.4 -3896.4 -3826.4 -3756.4 -3686.4 -3616.4 -3546.4 -3476.4
y +823.4 +823.4 +823.4 +823.4 +823.4 +823.4 +823.4 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 34
SYMBOL C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 C41 C42 C43 C44 C45 C46 C47 C48 C49 C50 C51 C52 C53 C54 C55 C56
PAD 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160
x -3406.4 -3336.4 -3266.4 -3196.4 -3126.4 -3056.4 -2986.4 -2916.4 -2846.4 -2776.4 -2706.4 -2636.4 -2566.4 -2496.4 -2426.4 -2356.4 -2216.4 -2146.4 -2076.4 -2006.4 -1936.4 -1866.4 -1796.4 -1726.4 -1656.4 -1586.4 -1516.4 -1446.4 -1376.4 -1306.4 -1236.4 -1166.4 -1096.4 -1026.4 -956.4 -886.4 -816.4 -746.4 -676.4 -606.4 -536.4
y -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7
Philips Semiconductors
Product specification
34 x 128 pixel matrix driver
PCF8531
SYMBOL C57 C58 C59 C60 C61 C62 C63 C64 C65 C66 C67 C68 C69 C70 C71 C72 C73 C74 C75 C76 C77 C78 C79 C80 C81 C82 C83 C84 C85 C86 C87 C88 C89 C90 C91 C92 C93 C94 C95 C96 C97 2000 Feb 11
PAD 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201
x -466.4 -396.4 -326.4 -256.4 -186.4 -116.4 -46.4 +93.6 +163.6 +233.6 +303.6 +373.6 +443.6 +513.6 +583.6 +653.6 +723.6 +793.6 +863.6 +933.6 +1003.6 +1073.6 +1143.6 +1213.6 +1283.6 +1353.6 +1423.6 +1493.6 +1563.6 +1633.6 +1703.6 +1773.6 +1843.6 +1913.6 +1983.6 +2053.6 +2123.6 +2193.6 +2263.6 +2403.6 +2473.6
y -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 35
SYMBOL C98 C99 C100 C101 C102 C103 C104 C105 C106 C107 C108 C109 C110 C111 C112 C113 C114 C115 C116 C117 C118 C119 C120 C121 C122 C123 C124 C125 C126 C127 R33 R31 R29 R27 R25 R23 R21 R19 R17 R15 R13
PAD 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242
x +2543.6 +2613.6 +2683.6 +2753.6 +2823.6 +2893.6 +2963.6 +3033.6 +3103.6 +3173.6 +3243.6 +3313.6 +3383.6 +3453.6 +3523.6 +3593.6 +3663.6 +3733.6 +3803.6 +3873.6 +3943.6 +4013.6 +4083.6 +4153.6 +4223.6 +4293.6 +4363.6 +4433.6 +4503.6 +4573.6 +4713.6 +4783.6 +4853.6 +4923.6 +4993.6 +5063.6 +5133.6 +5203.6 +5343.6 +5413.6 +5483.6
y -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7
Philips Semiconductors
Product specification
34 x 128 pixel matrix driver
PCF8531
SYMBOL R11 R9 R7 R5 R3 R1
PAD 243 244 245 246 247 248
x +5553.6 +5623.6 +5693.6 +5763.6 +5833.6 +5903.6
y -821.7 -821.7 -821.7 -821.7 -821.7 -821.7
handbook, halfpage
12.23 mm
Table 11 Bonding pads PAD Pad pitch Pad size; Al Bump dimensions SIZE min. 70 62 x 100 UNIT m m m
1.96 mm
PCF8531
pitch y
50 x 90 x 17.5 (5) m
x
MGS487
Wafer thickness (excluding 381 bumps) Table 12 Alignment marks MARKS C1 C2 F Circle 1 Circle 2 x -5402.0 +5292.4 +5890.3 -5543.0 +5637.4
y +823.1 +823.4 +401.9 +798.4 +798.4 Fig.26 Bonding pads.
handbook, full pagewidth
100 m
80 m
y center
100 m
y center
100 m
y center
100 m
x center circle
x center C
x center F
MGS490
Fig.27 Shapes of recognition pattern.
2000 Feb 11
36
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SDACK VSS1 VSS2 SCL ENR T2 T1 T3 T4 SA0
Philips Semiconductors
VLCDSENSE OSC
RES
VLCDOUT
VLCDIN
VDD1
VDD2
VDD3
SDA
handbook, full pagewidth
34 x 128 pixel matrix driver
PC8531-1
y
R0
R32 C0
MGS486
R1 pad1
C31 C32
C63 C64
C95 C96
C127 R33
37
The positioning of the bonding pads is not to scale.
0,0
x
. . .
. . .
. . .
. . .
. . .
Fig.28 Bonding pad location.
. . .
. . .
. . .
. . .
. . .
. . .
. . .
Product specification
PCF8531
Philips Semiconductors
Product specification
34 x 128 pixel matrix driver
16 DEVICE PROTECTION DIAGRAM For all diagrams: the maximum forward current is 5 mA and the maximum reverse voltage is 5 V.
PCF8531
handbook, full pagewidth
PADS 43 to 49
PADS 35 to 42
PADS 32 to 34
VDD1
VDD2
VDD3
VSS1
PADS 64 to 70
VSS1 VSS2
PADS 57 to 63
VSS1
PADS 57 to 63
PADS 16, 24 to 30
PADS 17 to 23
VSS2
VLCDIN (SUPPLY), VLCDSENSE VSS1
VLCDOUT
VSS1
VSS1
VDD1
PADS 73, 74, 50, 51, 52
VLCDIN
PADS 87 to 248
SCL, SDA, SDACK
VSS1
VSS1
VDD1
PADS 15, 54, 71, 72, 56, 31, 55
VDD1
PAD 78
OSC, SA0, T3, T1, T4, RES, ENR
T2
VSS1
MGS485
VSS1
Fig.29 Device protection diagrams.
2000 Feb 11
38
Philips Semiconductors
Product specification
34 x 128 pixel matrix driver
17 TRAY INFORMATION
PCF8531
handbook, full pagewidth
x
A
C
y D
B F
E
MGS488
The dimensions are given in Table 13.
Fig.30 Tray details.
Table 13 Dimensions DIM.
handbook, halfpage
DESCRIPTION pocket pitch; x direction pocket pitch; y direction pocket width; x direction pocket width; y direction tray width; x direction tray width; y direction
VALUE 13.72 mm 4.17 mm 12.34 mm 2.05 mm 50.8 mm 50.8 mm
A B C D E
PC8531-1
F x y
MGS489
number of pockets in x direction 3 number of pockets in y direction 10
The orientation of the IC in a pocket is indicated by the position of the IC type name on the die surface with respect to the chamfer on the upper left corner of the tray. Refer to the bonding pad location diagram for the orientating and position of the type name on the die surface.
Fig.31 Tray alignment.
2000 Feb 11
39
Philips Semiconductors
Product specification
34 x 128 pixel matrix driver
18 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
PCF8531
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 19 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 20 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
2000 Feb 11
40
Philips Semiconductors
Product specification
34 x 128 pixel matrix driver
NOTES
PCF8531
2000 Feb 11
41
Philips Semiconductors
Product specification
34 x 128 pixel matrix driver
NOTES
PCF8531
2000 Feb 11
42
Philips Semiconductors
Product specification
34 x 128 pixel matrix driver
NOTES
PCF8531
2000 Feb 11
43
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 2000
Internet: http://www.semiconductors.philips.com
SCA 69
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
465006/03/pp44
Date of release: 2000
Feb 11
Document order number:
9397 750 06616

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